<rss xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title>Vitis - Tag -</title><link>/tags/vitis/</link><description>Vitis - Tag -</description><generator>Hugo -- gohugo.io</generator><language>en</language><lastBuildDate>Mon, 03 Aug 2026 17:30:00 +0000</lastBuildDate><atom:link href="/tags/vitis/" rel="self" type="application/rss+xml"/><item><title>FPGA: Create a Custom IP with Vitis HLS 2025.2</title><link>/posts/vitis-hls-custom-ip/</link><pubDate>Mon, 03 Aug 2026 17:30:00 +0000</pubDate><author>Jack Bonnell</author><guid>/posts/vitis-hls-custom-ip/</guid><description>This week I have been working on a USB camera to DisplayPort pipeline for the Ultra96-V2, with a custom grayscale filter sitting in the middle of the PL path. The idea was simple enough: take frames from a UVC webcam, push them through a Vitis HLS IP, and show the result on a DisplayPort monitor. Getting the HLS block, Vivado design, and PetaLinux stack to agree took a bit more patience than I expected.</description></item></channel></rss>