<rss xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title>Petalinux - Tag -</title><link>/tags/petalinux/</link><description>Petalinux - Tag -</description><generator>Hugo -- gohugo.io</generator><language>en</language><lastBuildDate>Fri, 07 Aug 2026 12:00:00 +0000</lastBuildDate><atom:link href="/tags/petalinux/" rel="self" type="application/rss+xml"/><item><title>FPGA: Creating a MIPI PL pipeline on the TE0950</title><link>/posts/te0950-mipi-pl-pipeline/</link><pubDate>Fri, 07 Aug 2026 12:00:00 +0000</pubDate><author>Jack Bonnell</author><guid>/posts/te0950-mipi-pl-pipeline/</guid><description>This week I have been bringing up a MIPI camera pipeline on the Trenz TE0950, taking frames from a Raspberry Pi Camera Module v2 (Sony IMX219) through the Versal PL and out over Ethernet to VLC. Getting Vivado 2024.2, the soft-reset / IRQ wiring, and PetaLinux’s V4L2 stack to agree took more patience than the block design alone suggests. Overview This project is on the 2024.2 Xilinx toolchain (Vivado + PetaLinux).</description></item></channel></rss>